Method, apparatus and system for an edge rate controlled output buffer

ABSTRACT

A circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

CROSS REFERENCES TO RELATED APPLICATIONS

This application claims priority from U.S. Provisional Patent Application No. 61/983,276 filed on Apr. 23, 2014, which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention generally relate to a method, apparatus and system for an edge rate controlled output buffer.

2. Description of the Related Art

Traditionally, low power and low voltage edge rate controlled buffers are inverter based output buffers. Such buffers tend to have high current peak due to shoot-through current, inductive supply noise due to large voltage drop and electromagnetic interference (EMI) due to high output edge switching rates.

It is also challenging to control edge rate over PVT due to non-linear edge rate behavior that is variable over process, voltage, and temperature (PVT). Current solutions show input current signal dependent propagation delay, which creates large and unexpected mismatch between falling and rising transition.

FIG. 1 is an embodiment of a prior art solution using inverter staggered type edge rate. In such a solution, this requires precise clock scheme is needed to control accurate edge rate. In addition, this open-loop solution is not suitable for large load change requirement because it is difficult to be load independent control. As a result, the edge rate varies not only input control signal, but also capacitive load.

FIG. 2 is another embodiment of a prior art solution. Such a solution is used to implement for input current, I_(IN1) and I_(IN2) of FIG. 2. Utilizing a simple feedback based buffer and having large Cdg non-linear capacitance of MP and MN causes the slope to be non-linear with a constant input signal. Hence, a large feedback cap (CF>>Cdg) must be used along with the large input current signal. This requires silicon large area and often creates large propagation delay in order to drive a large linear feedback capacitor (CF). Since there is no direct charge initialization of the feedback capacitor, the startup voltage mismatch between the drivers (MP or MN) and the feedback initial voltage creates signal dependent propagation delay. This signal dependent delay will cause the crossing point distortion in an eye diagram test. As a result, such a solution is unable to accurately initialize feedback capacitance over PVT in order to achieve signal insensitive propagation delay.

Therefore, there is a need for an accurate and improved control edge rate control over process, voltage and temperature that minimizes signal dependent startup time in order to achieve good signal integrity.

SUMMARY OF THE INVENTION

Embodiments of the present invention relate circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay. The circuit includes at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers, at least two second buffers for level shifting to the at least two first buffers, at least two voltage sources for initializing the stage of at least one of the first or the second buffer, and a current source generator coupled to the voltage source of the second buffers.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIG. 1 is an embodiment of a prior art solution using inverter staggered type edge rate;

FIG. 2 is another embodiment of a prior art solution using a separate feedback capacitor for MP and MN;

FIG. 3 is an embodiment depicting two buffers generating differential signaling;

FIG. 4 is an embodiment depicting a edge rate controlled output driver circuit; and

FIG. 5 is an embodiment depicting a system using an edge rate controlled output driver circuit.

DETAILED DESCRIPTION

The proposed solution proposes a method, apparatus and system of insensitive parasitic capacitance of the drivers for low voltage, low power applications that accurately controlling edge rate over process and temperature and provide for a signal independent propagation delay to help maintain good diffential signal integrity.

FIG. 3 is an embodiment depicting two buffers generating differential signaling, different startup time of drivers causing the crossing point to shift. As show in FIG. 3, turning-on time mismatch will largely vary the crossing point when two buffers generate differential signaling. Traditionally, trimming the input current does not solve the problem. In some cases, it may alleviate the trimming; however, it will vary over process, voltage, and temperature (PVT). This also causes the crossing point distortion, which is undesirable.

In differential signaling, the crossing point of two signals, Vout,p and Vout,n of FIG. 3, do not vary much over process, supply voltage, and temperature and is typically desired to have the crossing point in the middle of valid supply range for good signal integrity. In one embodiment, when trimming is used to meet edge rate specifications, there may be time delay associated with this trimming. This delay associated with trimming may cause the startup time of the amplifier, such that the crossing point may not occur at the desired crossing point range. In addition, this delay will vary across PVT.

FIG. 4 is an embodiment depicting an edge rate controlled output driver circuit. The proposed circuit has 4 states, State0-State3, which are: State0: Low to high transition: S1, S2, S8, and S7 switches are closed, State1: High output: S1,S2, S3, and S8 switches are closed (Vp=Vthn), State2: High to low transition: S5, S6, S3, and S4 are closed, and State3: Low output: S5, S6, S7, and S4 are closed (Vp=Vthp). In order to remove signal dependent propagation delay and to minimize propagation delay, Vp needs to be equal to Vthp at the beginning of state0 and Vp needs to be equal to Vthn at the beginning of state2.

In FIG. 4, MN2 and MP2 are buffers, which are used to decouple large nonlinear parasitic Cgd of each driver from CFB (e.g., Cdg>5-10× C_(FB)). MN3 and MP3 are also buffers used to do level shifting to help for low voltage applications (canceling the required voltage due to the buffer (MN2 and MP2). The gate-source voltages of MN2/MP3 and MP2/MN3 are largely canceling out each other so that the required gate-source voltage of MN1/MP1 can be shown at the node Vp.

In one embodiment, the current source generator, such as, lin1 and lin2, may be converted into a voltage generator once the output rails out. This was done by cascading device with gate-source connected device. For example, the bold black line path is activated, such as, S1 and S2 are on. MP1 and CFB form capacitive feedback amplifier with a constant current to generate desired slew controlled output. Note that the node Vp is constant during slew controlled swing region because the circuit works as an integrator. After Vout swing reaches the positive rail, VDD, the switch S3 on and Vp is defined to Vthn (e.g., MN1 threshold voltage) rather than ground. In one embodiment, there were no gate-source connected device, Vp node voltage would go close to ground so that the voltage across the feedback would be VDD.

In one embodiment, S3 switch action is automatic and implemented in the same gate-source connected device here in order to initialize charges on the feedback capacitor for signal independent startup of the drivers. Once Vp node goes below the current reference voltage, the gate-source connected device becomes a diode-connected device such that Vp node can be defined to Vthn (e.g., MN1 device threshold voltage.) Since MN1 driver will be on next signal, the initial voltage across the feedback capacitor is VDD-Vthn, which is desired to remove signal dependent startup.

FIG. 5 is an embodiment depicting a system using an edge rate controlled output driver circuit. The system of FIG. 5 is any system that requires an edge rate controlled output driver applications. Such a system benefits from controlling the edge rate of output signals that generated by a transmitter or driver to eliminate any high order of harmonics to reduce EMI/EMC emission. The following are examples of such systems: USB 1.1 and USB 2.0 type of signaling drivers or any edge rate controlled digital data communication physical layer drivers, any capacitive touch screen controller drivers, and the likes.

As shown in FIG. 5, the transistor includes a gate-source connected device. The gate will be in “Off state” during transition. Once the output rails out and ready for the next signal, the gate-source connected device cancels the gate-source voltage of MN_I_IN_REF_CC2 so that the node I_(NN1) is defined close to Vthn. MN1 and the current source, lin2, are the same type of the device in order for their threshold voltage can track well over PVT. When MN1 is on, the node Vp is initialized to Vthn to prevent the need to equalize the charge stored on the feedback capacitor (CFB). As a result, MN1 amplifier on has a quick start up time with no signal dependent propagation delay.

The proposed solution minimizes variation over PVT for edge rate over and propagation delay. As a result, the improved circuit leads to a robust solution over PVT, signal independent propagation delay, low quiescent current consumption, low supply solution, insensitive to nonlinear driver device capacitance, small form-factor, load insensitive edge rate control, minimize undesirable handoff transient response, etc.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. 

What is claimed is:
 1. A circuit for minimizing variation over process, voltage and temperature for edge rate over and signal independent propagation delay, comprising: at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers; at least two second buffers for level shifting to the at least two first buffers; and at least two voltage sources for initializing the stage of at least one of the first or the second buffer; and a current source generator coupled to the voltage source of the second buffers.
 2. The circuit of claim 1, wherein the circuit provides for 4 states, low to high transition state, high output state, high to low transition state, and low output state.
 3. The circuit of claim 1, wherein the circuit removes signal dependent propagation delay and minimizes propagation delay.
 4. A system for controlling the edge rate of output signals to eliminate any high order of harmonics to reduce EMI/EMC emission comprising a circuit for minimizing variation over process, voltage and temperature for edge rate over and propagation delay, the circuit comprises: at least two first buffers for decoupling large nonlinear parasitic capacitors of the main drivers; at least two second buffers for level shifting to the at least two first buffers; and at least two voltage sources for initializing the stage of at least one of the first or the second buffer; and a current source generator coupled to the voltage source of the second buffers.
 5. The system of claim 4, wherein the circuit provides for 4 states, low to high transition state, high output state, high to low transition state, and low output state.
 6. The system of claim 4, wherein the circuit removes signal dependent propagation delay and minimizes propagation delay. 